IC packaging, typically an afterthought in the design of a new-generation SoC, is particularly troublesome for communications circuits and high-speed interface circuits. Everyone wants small size and ...

OrbitIO interconnect designer capabilities deliver hierarchical multi-substrate-optimized design for SoCs and ASICs across IC package/SiP and systems SAN JOSE, Calif., May. 04, 2016 – Cadence Design ...

For many applications, next generation IC packaging is the best path to achieve silicon scaling, functional density, and heterogeneous integration while reducing the overall package size.

Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized ...

As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides ...