EDN

CN0290: Extending the Low Frequency Range of a High Performance Phase Locked Loop

The circuit shown in Figure 1 is a high performance phase locked loop (PLL) that uses high speed clock buffers and low noise LDOs to maintain low phase noise even at low reference and RF frequencies.
EDN

Phase-locked Loop with Linear VCO

The HEF4046B is a phase-locked loop circuit that contains a linear voltage-controlled oscillator (VCO) and two discrete phase comparators that has a common signal input amplifier and a common ...
Nature

Compact devices, optical phase-locked loops and more

Microwave Photonic Systems (West Chester, Pennsylvania, USA) has released a range of new transmitters and receivers that are designed to suit incorporation into radiofrequency (RF) photonic transport ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 2)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
Electronic Design

Measure Phase-Locked Loops With A Spectrum Analyzer

A general-purpose vector signal analyzer offers a low-cost, flexible option for measuring the frequency settling time of PLLs. By Douglas Olney, Keithley Instruments Inc. The frequency-settling time ...